How does a DSP/FPGA phase accumulator work?

Question

I'm looking at the code for a phase accumulator, and I must be a simpleton because I don't get it. The code is simple enough:

  Every Clock Tick do:
    accum = accum + NCO_param;
    return accum;

accum is a 32-bit register. Obviously, at some point it will roll-over.

My question really is: How does this relate to the phase?

Answer 1

This article may help.

In the running step, the counter (properly called the phase accumulator) is instructed to advance by a certain increment on each pulse from the frequency reference. The output of the phase accumulator (the phase) is used to select each item in the data table in turn. Finally, the DAC converts this sequence of data to an analogue waveform.

In the running step, the counter (properly called the phase accumulator) is instructed to advance by a certain increment on each pulse from the frequency reference. The output of the phase accumulator (the phase) is used to select each item in the data table in turn. Finally, the DAC converts this sequence of data to an analogue waveform. To generate a periodic waveform, the circuit is set up so that one pass through the table takes a time equal to the period of the waveform. For example, if the reference frequency is 1 MHz, and the table contains 1000 entries, then a complete pass through the table with a phase increment of 1 will take 1000 / 1 MHz = 1 ms, so the frequency of the output waveform will be 1/(1 ms) = 1 kHz.

This system can generate a higher output frequency simply by increasing the phase increment so that the counter runs through the table more quickly. In the example above, the phase increment is equal to 1, so the next possible frequency is obtained by setting the increment to 2, resulting in a doubling of output frequency. To obtain a finer control of frequency than this, the standard phase increment can be set to, say, 10. This then allows slightly higher or lower output frequencies. For example, increasing the increment to 11 would increase the output frequency by 10%, and reducing it to 9 would decrease the output frequency by the same proportion. The more precision required over the frequency, the more bits are needed in the counter.

Answer 2

Answering my own question, I found another interesting article online describing a phase accumulator for frequency synthesis.

Here is my understanding of how the phase accumulator works:
The accumulator register actually represents 360 degrees. Thus, a value of 0 represents 0 degree, a value of 2^32 represents 360 degrees.

The phase accumulator adds a value (M) every clock tick. This represents the angle moving around the circle by (M/2^32) degrees. When the register overflows, we simply cycled through a full 360 degree and start over.

Answer 3

The formula is this:

Example using oscillors that have a period of waveform(x) period = x(0-1) rather than x(0-2Pi)

One variable per audio stream called acc/accumulator,

Every sample, accumulate it by accadd:

    var accadd = 1.0/( sampleRate / p2freq( note ) ) ;
    acc+= accadd;
    acc = acc%1.0;// not sure to do this as accurately using if statement. can reset acc every noteOn

If you are using classical Sin with 2pi period, use 2pi instead of 1.0

Like that the waveform will run from 0-1 at p2freq(note) periods per second.