My program works in ModelSim, but doesn't work on real FPGA board

Question

There is my VHDL code, and there is BDF desing.

When I simulate my VHDL code in ModelSim, it's working fine, but when I simulate it in Quartus or upload to FPGA Cyclone board, LED have no signal. IDK, in what way I suppose to look at.

Answer 1

I had a quick look at your code, and while it seems syntactically correct, it doesn't really look synthesizable (even though it may be).

For example:

led_size : process(clk, size)
begin
  if size = '1' then     
    led_size_f <= led_size_f +1;
  end if;
  if  led_size_f > 4 then 
    led_size_f <=1;
  end if;
end process;

It doesn't even use clk, and it will also generate a latch (generally a bad thing, unless you're absolutely certain what you're doing), which will most probably give you problems when trying to run it in an FPGA.

I can post more examples, but if I were you, I'd try looking at the list of warnings that you're most probably getting from your synthesis tool.

Also, see if your IDE comes with some templates for synchronous design, and then try to adhere to them, to make sure that you are actually inferring the hardware that you want.