Cannot compile unisim code in iverilog

Question

I have been trying to compile ICAP_SPARTAN6.v from the unisim librabries provided by xilinx using icarus verilog.

I get the compile error below:

/opt/Xilinx/14.3/ISE_DS/ISE/verilog/src/unisims/ICAP_SPARTAN6.v:79: syntax error
/opt/Xilinx/14.3/ISE_DS/ISE/verilog/src/unisims/ICAP_SPARTAN6.v:79: error: invalid module item.

The relevent lines of code referred to is below:

  tri (weak1, strong0) done_o = p_up;//line 78
  tri (pull1, supply0) [15:0] di_t = (icap_idone == 1 && WRITE == 1)? 16'bz : dix; //line 79

I would also like to note that I am not very clear how tri works exactly. I assumed that it is similar to a wire except has 3 states but the paranthesis following it does not make sense to me and that makes debugging a little harder :) Any help would be appreciated. -Thanks

Answer 1

tri and wire are equivalent.

The keywords in parentheses determine drive strength, which allows switch and gate-level modeling. The rules are somewhat complex but basically a stronger signal can override a weaker one so driving a pull1 and strong0 on the same signal may result in a 0 state, rather than X or Z.

The error looks like a bug or missing feature in iverilog. Removing the vector range allows a successful compile.