- Exception handlers should not re-enable exceptions until after they have saved EPC, SR etc.
- The software interrupts are exceptions.
- Some MIPS CPUs have been built with different interrupt and exception vectors, but this turns out not to be very useful.
- MIPS has precise exceptions: i.e. exceptions appear in instruction sequence and only the first exception in the pipeline will be architecturally visible.
See MIPS Run Linux is the best and most readable reference for MIPS exceptions and the MIPS PRA.