In verilog, you can only assign a value to a reg
in always
or initial
blocks. You've also got the bit range for stripping bits from you RGB
bus on the wrong side of the bus name.
reg [5:0] r;
always @(RGB) begin
r = {bi7, RGB[15:11]};
end
Note that in verilog, parameter names such as bi7
in your code, are usually defined and written in UPPER CASE to make them easy to pick out.