VHDL - type declaration in package

Question

I am trying to scroll a text on the 7 segment display. The text will be entered from a keyboard and I am using BASYS2 as FPGA. My keyboard interface is done, as well as my seven segment controller. But I am having problems with my shifter module. As I'm dealing with scancodes, I need to use an array of bytes. I declared such type in a package, that is "mypackage2". However, as far as I understood, the shifter module is unable to use that type, namely "reg_array". What do I need to change, or is there something I am missing here? As I'm new to VHDL, I might have done some basic errors. Also, the package I've written does not show up in the project hierarchy at the lefthand side of the window. Any help is appreciated. Thank you.

EDIT: I noticed that I shouldn't use reg array as follows: Data_out : out reg_array(REGSIZE-1 downto 0), because its width is already specified. So I changed my code a little bit and reduced the number of errors to 3.

Here's the shifter module:

library IEEE; 
use IEEE.STD_LOGIC_1164.ALL; 
use IEEE.STD_LOGIC_UNSIGNED.ALL; 
use IEEE.STD_LOGIC_ARITH.ALL; 
use work.mypackage2.all; 

entity shifter is 
    generic ( REGSIZE  : integer := 16); -- Text will be composed of 16 characters
    port(clk      : in  std_logic; 
         Scan_Dav : in  std_logic; -- this is '1' when there is a new scancode
         Data_in  : in  std_logic_vector(7 downto 0); --scancode from keyboard
         Data_out : out reg_array ); 
end shifter; 

architecture bhv of shifter is 

        signal shift_reg : reg_array;
begin 
    process (clk, Scan_Dav) begin 
        if rising_edge(clk) then 
            if Scan_Dav = '1' then 
                shift_reg(REGSIZE-1 downto 1) <= shift_reg(REGSIZE-2 downto 0); 
                shift_reg(15) <= shift_reg(0); 
            end if; 
        end if; 
        Data_out <= shift_reg; 
    end process; 
end bhv; 

Here's the package:

library IEEE; 
use IEEE.STD_LOGIC_1164.all; 

package mypackage2 is 

   subtype reg is std_logic_vector(7 downto 0); -- a byte 
        type reg_array is array (0 to 15) of reg; -- array of bytes 

end mypackage2; 


package body mypackage2 is 

end mypackage2; 

And these are the latest errors:

ERROR:HDLParsers:807 - "F:/Projeilk/Shifter.vhd" Line 22. shift_reg can not be used with range downto.
ERROR:HDLParsers:807 - "F:/Projeilk/Shifter.vhd" Line 22. shift_reg can not be used with range downto.

Answer 1

You've defined the size of the byte array twice. In the package file, you've defined reg_array as a fixed array of 16 reg's. But in the architecture, you're trying to specify the size of shift_reg by defining the size of reg_array again with (REGSIZE-1 downto 0) as if reg_array was a variable-sized array.

You can either keep the fixed declaration of reg_array and define shift_reg as:

signal shift_reg : reg_array;

Or keep your definition of shift_reg and declare reg_array as a variable-width array like:

type reg_array is array (natural range <>) of reg; -- variable-length array of bytes 

It looks like you may have a few more errors in the code, but some of them may be cascading from this problem.

Answer 2

I'm unable to add comments yet, so I'll have to add another answer. Looking quickly, I don't see anything strictly wrong with your top-level. I suspect the RTL output is the victim of optimization. Specifically, are the outputs of KeyboardController being optimized away in synthesis? The DoRead input is not driven, which may be the cause, but without peeking at the KeyboardController code, its only a hunch.

Answer 3

CONTINUED ( NEW PROBLEM)

I will continue from here instead of opening a new topic. If I am wrong doing so, please correct my mistake.

All my code compiled successfully, but I think there is an inconsistency with what I wrote and what schematic shows.

This is my top level module:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.mypackage2.all;

entity TopModule is
    generic ( REGSIZE  : integer := 16);
    Port (Clk        : in STD_LOGIC;
            Reset      : in std_logic; -- System Reset
            PS2_Clk    : in std_logic; -- Keyboard Clock Line
            PS2_Data   : in std_logic; -- Keyboard Data Line
            ANODES     : out STD_LOGIC_VECTOR(3 downto 0);
            SEGMENTS   : out STD_LOGIC_VECTOR(6 downto 0));
end TopModule;

architecture Top_arch of TopModule is

    component clkdivide is
        Port (clkin: in std_logic;
                clkout:out std_logic );
    end component;

    component SevenSegmentController is
        Port (  CLK: in std_logic;
                    DEC1, DEC2, DEC3, DEC4: in std_logic_vector(7 downto 0);
                    SEGMENTS: out std_logic_vector(6 downto 0);
                    ANODES: out std_logic_vector(3 downto 0));
    end component;

    component KeyboardController is
        port (Clk : in std_logic; -- System Clock
                Reset : in std_logic; -- System Reset
                PS2_Clk : in std_logic; -- Keyboard Clock Line
                PS2_Data : in std_logic; -- Keyboard Data Line
                DoRead : in std_logic; -- From outside when reading the scan code
                Scan_Err : out std_logic; -- To outside : Parity or Overflow error
                Scan_DAV : out std_logic; -- To outside when a scan code has arrived
                Scan_Out : out std_logic_vector(7 downto 0));
    end component;

    component shifter is
        port (clk      : in  std_logic;
                Scan_Dav : in  std_logic;
                Data_in  : in  std_logic_vector(7 downto 0);
                Data_out : out reg_array );
    end component;

    signal clk2, scandav, scanerr, doread: std_logic;
    signal sarray: reg_array;
    signal datain: std_logic_vector(7 downto 0);

    begin
        L1: SevenSegmentController 
            port map (SEGMENTS=> SEGMENTS, CLK=> clk2, ANODES=> ANODES,
            DEC1=> sarray(15), DEC2=> sarray(14),
            DEC3=> sarray(13),DEC4=> sarray(12));

        L2: clkdivide 
            port map (clkin=>Clk , clkout=>clk2);

        L3: KeyboardController 
            port map (Clk=> clk2, Reset=> Reset, PS2_Clk=> PS2_Clk,
            PS2_Data=> PS2_Data, DoRead=> doread, Scan_Err=> scanerr,
            Scan_DAV=> scandav, Scan_Out=>datain);

        L4: shifter
            port map (clk=>clk2, Scan_Dav=>scandav, Data_in=> datain, 
            Data_out=>sarray);
end Top_arch;

This is the RTL schematic:

The components are not linked with each other, keyboard interface's output should be directed to shifter, and then shifter to seven segment controller, but shifter is all by itself. What is the problem here?