Undesiderated 1-bit latch (VHDL)

Question

I'm programming a N-bit non-restoring divider, but I faced a little problem.

I have an Operative Part (combinatorial) and a Control Part (Finite State Machine). The Control Part has a 2 processes FSM, 1 for updating the next state and 1 for the "state sequence".

update:     process(clk_in, next_state)
        begin
            if rising_edge(clk_in) then
                current_state <= next_state;
            end if;
        end process;

And this is the second process:

control:    process(current_state, start, S_in, counted)
            variable sub_tmp : STD_LOGIC := '0';
        begin
                            [...]
            sub <= sub_tmp; -- sub is an output signal of my entity that goes in the Operative Part

            case current_state is
                when idle =>
                    if start='1' then
                        next_state <= init;
                    else
                        next_state <= idle;
                    end if;

                when init =>
                                            -- [...]
                    next_state <= subtract;

                when subtract =>
                    en_A <= '1';
                    sub_tmp := '1';
                    next_state <= test;

                when test => -- shift
                    en_Q <= '1';

                    if S_in='0' then
                        sub_tmp := '1';
                    else
                        sub_tmp := '0';
                    end if;

                    if counted=N/2-1 then
                        next_state <= finished;
                    else
                        next_state <= operation;
                    end if;

                when operation =>
                    en_A <= '1';
                    next_state <= test;

                when finished =>
                    stop <= '1';
                    next_state <= idle;
            end case;
        end process;

As you can see, I need to change the value of the sub ONLY in 2 cases (subtract and test), while I don't have to change in the other cases.

The problem is that when I try to synthesize this code it turns out that sub_tmp is a LATCH, but I don't want a latch. I need to do something like this:

state 1 => set sub to '1' or '0' (depending on another input)

state 2 => do other operations (but sub must remain the value set before) and return to state 1 etc...

To clarify more: in certain states of my FSM (not all of them) I set the value of a variable (let's call it sub_tmp). In other states I don't change its value. Then let's say I have an output PIN called "sub_out". Now, independently of the variable value, I want to output its value to this pin (sub_out <= sub_tmp; or similar).

What am I missing?

Answer 1

What you are missing is the behavior you describe IS a latch. Anything with memory (ie: "in other states I don't change it's value") is either a latch or a register (flip-flop). If you don't want a latch or a register, you need to assign a specific value to the signal in each and every code path, and not let it 'remember' it's previous state.