Question

Consider the instruction MVI A,32H to load 32H in the register A (Intel 8085 Microprocessor).

My book says that it is a two byte instruction where the first byte is the opcode and the second is the operand. The first byte being 0011 1110 (3E in hexadecimal) and the second byte being 0011 0010 (32 in hexadecimal).

I am confused as to how exactly the opcode part is converted into machine code. I mean... what part of the "0011 1110" stand for "MVI" and what part of it tells that register A is to be loaded? How does "3E" tell the microprocessor both the information? That is it has to load data as well as the target register. Or is it that this entire opcode is predefined and you can't separate the "MVI" and "target register" in the opcode?

I hope my question makes sense lol.

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Solution

http://www.pastraiser.com/cpu/i8085/i8085_opcodes.html

The whole thing 0x3E means MVI A.

From the table in the link above (assuming it can be trusted)

0x0E MVI C  00001110
0x1E MVI E  00011110
0x2E MVI L  00101110
0x3E MVI A  00111110

0x06 MVI B  00000110
0x16 MVI D  00010110
0x26 MVI H  00100110
0x36 MVI M  00110110

The color coding on that chart gives a strong indication of the opcode decoder if the 2 msbits are 00 then if the lower 2 bits are 10 then if bit 2 is a 1 then it is an MVI and bits 3-6 determine which register. basically 0b00rrr110 is an MVI.

OTHER TIPS

Improving upon the answer given here. MVI R,d8 loads the supplied 8-bit data (d8) into the specified register or memory loaction (R). There are eight possible choice for R namely B, C, D, E, H, L, M, and A. These eight possibilities can be encoded with three bits as follows.

name | code
-----|-----
  B  | 000
  C  | 001
  D  | 010
  E  | 011
  H  | 100
  L  | 101
  M  | 110
  A  | 111

MVI R,d8 encodes the register name into the 8-bit opcode itself as 00rrr110 where rrr stands for the 3-bit code of the register as shown in the above table. Thus MVI A,32H will result into its first byte (opcode) being 00 111 110 or 0x3E and second byte (data) being 0x32.

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