When the simulator is compiling the toplevel (DE2_TOP) it want to know how the used components are like. So, you should have compiled the lowerlevel components before compiling the upperlevel components.
What I do most of the times to fix this is compiling all components in correct order and then use the 'vmake' ('vmake -work work > work.vmake') command of Modelsim to generate a makefile out of the library (work). Once you have the makefile you can execute it with (make -f work.vmake). And all files will be compiled in order.
Note: Verilog is much more relaxed in those things...