If there exists two component of same name, one in package and other in architecture, which one is given priority?

Question

I have a VHDL test file a.vhd.

cat a.vhd

package pak is
component b is              -- 1st definition of component b.
end component
end pak;

use work.pak.all;          -- 1st definition visible through this package use clause
entity a is
  port (in1 : in std_logic );
end a;

architecture a of a is

component b                   -- 2nd definition of component b.
  port ( in11 : in std_logic);
end component;

begin
  inst : b port map ( in11=> in1);   -- there are two definitions of component b at this instance.
end a;

entity b is
port (in11 : in std_logic);
end b;

architecture b of b is
begin
end b;

So, when running modelsim on it, there was no warning/error of overridden component. Do we always give preference to the component, which is declared in the architecture over the component of same name declared in package. Can somebody tell me what does LRM say about it? Please explain this.

Answer 1

In this specific example, the component you instantiate in "a" as "inst" is certain to be the component "b" declared in the architecture, because work.pak.b has a different port declaration.

If you instantiated a "b" with no ports in A, you should see work.pack.b.

Understand however that there is no inherent link between EITHER of these and "entity b". Only when the design is elaborated (e.g. at the start of simulation) will the tools look for a "b" that actually matches the component declarations. In this case it can find "b" declared in "a", but it won't find an entity matching "work.pak.b".

At this stage you can use configurations (either separate configurations, or configuration statements embedded in arch A) to bind a specific entity "work.b" to "b". This won't work with "work.pak.b" because of the mismatched port declarations.