If I understand your question, you want to know how to generate a zero value with the same width as data_stack
?
In that case, use the replication operator:
data_stack = {DATA_WIDTH{1'b0}};
This generates DATA_WIDTH
number of zeros.
Question
How do I nullify a register in SystemVerilog if I do not know the size? For example, if I have:
reg [DATA_WIDTH-1:0] data_stack;
with some parameter DATA_WIDTH
given to the module. Is it possible to assign a zero to the register data_stack
?
Note that it is sufficient to initialize a similar reg
to zero as then I can simply perform a bitwise and between the two and nullify data_stack
.
Solution 2
If I understand your question, you want to know how to generate a zero value with the same width as data_stack
?
In that case, use the replication operator:
data_stack = {DATA_WIDTH{1'b0}};
This generates DATA_WIDTH
number of zeros.
OTHER TIPS
The IEEE Std 1800-2009 is the golden reference. The following sets all bits to 0:
data_stack = '0;
Refer to the section "Integer literal constants".
An unsized single-bit value can be specified by preceding the single-bit value with an apostrophe ( ' ), but without the base specifier. All bits of the unsized value shall be set to the value of the specified bit. In a self-determined context, an unsized single-bit value shall have a width of 1 bit, and the value shall be treated as unsigned.
I think your searches would yield better results if you searched for initialising registers, instead of nullify.
If this is a testbench variable then just :
initial begin
data_stack = {DATA_WIDTH{1'b0}};
end
If it is to be used in a flip-flop you need to reset it:
always @(posedge clk or negedge reset_n) begin
if (~reset_n) begin
data_stack <= {DATA_WIDTH{1'b0}};
end
else begin
//<=nextvalue;
end
end