What can be adjusted in this simple code to make signal change in fsm

Question

Well i have process a in my main component and process b in my other sub component(inmplemented in the main one). both process a and b have only the clock in their sensitivity list: process a control eneable signal called ready which if 1 process b can work , 0 process b will do nothing. Problem is in process a , when process a changes value of enable signal to 0 , it has to take to the next clock cycle to change so process b ends up and run an extra clock cycle.

a:process(clk)
begin
if(rising_edge(clk)) then
if(output/=old_output) then
        enable<='0';
end if;
end if;
end process;

b:process(clk)
begin
if(rising_edge(clk)) then
if(enable='1') then
        --do anything
end if;
end if;
end process;

Answer 1

The reason is that the value is latched/sampled at the exact rising_edge of the clock. At that time, 'enable' is still equal to one. In that simulation delta, enabled will get the value zero, but it won't be available until AFTER the first delta.

This is also true for when enable BECOMES one (given that it is also generated on a rising clock edge), the process will latch the value exactly when clock rises, and in the simulator, enabled will look high for a whole clock period, even though "--do anything" will not happen.

You can think of this as real electrical circuits instead of a programming language. Consider that the evaluation of "output/=old_output" will consume time, and that you as a designer want that to be DONE before the next rising clock edge.

Hope this helps, but this is how the language works. I could give you a better answer if both the setting and resetting of the enable.