Wires are not connected in the RTL

Question

I have some strange problem, some wires are not connected in my design.

I am trying to make a simple register file (I am using Xilinx ISE). This register file contains 32 registers, each is 32-bit size. The register file has two MUXs for reading selection (2 readings in parallel), and a decoder for write selection. When I try to connect signals from each register to the 2 MUXs, the signals appear in the RTL connected to only one of the MUXs. For example, let signal reg2out be the output of reg2. I connect reg2out to pin I1 of mux1, and connect again reg2out to pin I1 of mux2. The RTL then shows the second mux connected correctly, but the first mux appears with no inputs, no selectors, and no output connected to it. The next image shows the RTL.

Note: ISE generates the following warning when synthesizing

"WARNING:Xst:1348 - Unit mux is merged (output interface has tristates)"

which I don't understand.

The main module source "RegisterFile.vhd" can be found here. I have tried a dozen of modifications to correct, including adding new signals, storing the registers output in D-FFs, and storing the registers output in process variables; and the problem still existing. The design contains two other files: "dec.vhd", and "mux.vhd". I believe the design of these modules is correct.

How can I correct the problem? Is it a bug in ISE rather?

Answer 1

it is a bug in ISE 12.1. however, it seems that it is only a bug in RTL schematic visualization, as the synthesis report mentions the used components correctly. using ISE version 12.2, the issue is not reproducible anymore.