Parallel To Serial HDL

Question

I am making a parallel to serial converter using ring counter in verilog. The ring counter is working fine but the Parallel to serial converter is not working properly and I am getting x undefined result. I am providing the code kindly help me finding the problem.

TOP

module PtoSTOP;

  reg clk,rst;

  wire [3:0] myout;
  wire       out;

  Ring a(clk,rst,myout);

  parToser x(myout,clk,rst,out);

  initial begin 
    clk=1;
    rst=1;

    #1 rst=0; 
 end

 always
   #2 clk=~clk;

 endmodule

Parallel TO Serial Converter

module parToser(myout,clk,rst,out);

input clk,rst;
input [3:0] myout;
output reg  out;

reg [2:0]i;

always @(posedge clk or posedge rst) begin
  if(rst) begin
    out <= 0;
    i   <= 0;
 end
 else begin
   out <= myout[i];
   i   <= i+1;
  end
end

endmodule 

RingCounter

module Ring(clk,rst,myout);

input clk,rst;
output reg [3:0]myout;

always @(posedge clk or posedge rst) begin
  if(rst)
    myout<=1;
  else
    myout<=myout<<1;
end

 endmodule

Answer 1

I think the main issue you are seeing is part of parToser.

You have reg [2:0]i; which you increment and use to address input [3:0] myout; but i can hold values 0 to 7, half of which is outside the address range of [3:0] myout. You should be seeing a simulation error about out of range addressing.

Also you have included a few flip-flops with a reset condition but not added the reset to the sensitivity list in 'parToser' & 'Ring':

always @(posedge clk) 

Should be:

always @(posedge clk or posedge rst)

With out this trigger your out, i and myout variables will be x, as they have not been set to a known condition.

NB: parToser i = i+1; should be i <= i+1;