array and multiplexer in Verilog

Question

I am curious to know how an array in synthesized in verilog. Does it creates a MUX of the size of array or something else. Is there some technique to avoid large size MUX synthesize.

Answer 1

If the array is read-only, then it will be implemented as a ROM (or a RAM with the write-enable disabled!)

If the array is writable, then there a rules about how the writes occur to ensure that a RAM block is inferred.

Answer 2

Generally large arrays might be synthesized as dynamic rams (depending on your synthesis options), but they could also be implemented as a giant field of flip flops with a large mux if you prefer, but using dynamic rams would be the most area efficient way to synthesize a large array.

Do note if dynamic rams are used then you'll generally be restricted to one or two reads or writes per cycle (can't update every entry in the ram at once).