Mealy and Moore implementations in verilog

Question

Can any one tell what are the differences between these implementations in verilog/VHDl? I mean how does Mealy and Moore Synthesize into circuits in detail ? Any links would prove useful too. I am quite familiar to this

Thank you

But is this the way it implements ??

Answer 1

The synthesiser will implement logic that matches the code you have written. If you have outputs which are unregistered (ie, not written to from a clocked block) then that's what the synthesiser will give you.

More to the point - why does anyone care? Academics seem to keep teaching Mealy vs Moore for no good reason I can see. In my getting on for 2 decades of professional electronic design, I have never had to care what "kind" of state machine I am getting. I just describe the behaviour and let the tools produce the circuits. The tools also do not care (check the logfiles, it won't say "found a Mealy state-machine" anywhere).

Answer 2

whether or not the synthesizer recognizes your code as FSM and also the way it implements FSMs in hardware depends on the synthesizer you use! check the according documentation. e.g. for Xilinx XST, see the XST user Guide, and search for FSM.

Answer 3

I know this is 3 weeks old, but there's an answer here, with details of what the various styles synthesise to in XST. The example is actually a Moore machine, but some of the styles have combinatorial outputs, which will give you an idea of what will happen for Mealy machines. There are some surprises - XST can push combinatorial outputs back into state registers, for example.