VHDL: Properly clocking another component with respect to setup

Question

I am working on a FPGA project in VHDL.

I need to copy a 16 bit shift register into a FIFO each time it fills up (eg after 16 new data bits have been fed into the shift register, I want to take the newly formed 16 bit word and send it to a fifo)

My question is, do I need to set up the data at the input of the fifo one clock before asserting the clock line on the fifo? This is actually a generic VHDL question, and not specific to fifos.

Basically, is it possible to set the data and toggle the clock in the same operation, or do I need some basic state machine to set up the data on one clock edge and toggle the fifo clock on the next?

for instance:

fifo_d_in( 7 downto 0 ) <= shift_register;
fifo_clk <= '1';

or

if( state = one ) then
    fifo_d_in( 7 downto 0 ) <= shift_register;
    state <= two;
elsif( state = two ) then
    fifo_clk <= '1';
end if;

My gut tells me that I have to setup the data first, to satisfy the setup & hold requirements of the input registers.

Thanks!

Answer 1

The data must be present for the setup time before the clock edge, so asserting the clock at the same time as any possible data changes may result in unstable behaviour.

One way to configure your shift register is to have an output which asserts after the last bit of data has been clocked in. For an 8 bit shift register, after the 8th clock the signal would be asserted. Any easy way to accomplish this is with a 3 bit counter, when all bits are 1 the output is 1. This signal is then connected to the CLKEN of your fifo so that on the 9th clock edge, the data at the output of your shift register is clocked into the the fifo. It would also be possible to clock in the next serial bit of data to your shift register on the 9th clock.

       shift reg             FIFO
       -------------        ---------
      -|DIN   DOUT |--------| DIN   |
       |      FULL |--------| CLKEN |
     - |>          |      --|>      |
     | -------------      | ---------
     |                    | 
CLK -----------------------

In the above diagram, FULL would be asserted the instant after the last bit of data was clocked in to fill the shift register, and deasserted on the next cycle. FULL can be combinatorial logic.