Does mips branch delay slots propagates through successive branches?

Question

I was playing around with branch delay slots. Tried that on spim.

j some
j a 
j b 
j c 
j d 
ori $9, $0, 13

some:
a:  
b:  
c:  
d:  

For my surprise it changed the $9 to 13. So my question is can a delay slot propagate or this is a spim thing and doesn't happen on real mips32 processors? If this is the expected behavior can someone give me a little enlightenment on what's happening there?

Answer 1

As a disclaimer, I've never worked with a real MIPS machine, but I imagine that using a branch delay slot for another branch will almost certainly cause problems. One common practice on processors like MIPS is to use the branch delay slot for a no-op, such as ori $0, $0, 0, just to make sure that nothing executes that isn't supposed to.

Answer 2

Mips states that placing branch instruction in to a branch delay slot leads to undefined results.