Question

I was reading the source code for the model-specific register (MSR) driver kernel extension that ships with the Intel Performance Counter Monitor (http://software.intel.com/en-us/articles/intel-performance-counter-monitor-a-better-way-to-measure-cpu-utilization). Since independent copies of the MSRs/performance counters are stored on different CPUs, it is necessary to specify which CPU to read from. This is done by calling the mp_rendezvous_no_intrs function.

mp_rendezvous_no_intrs(cpuReadMSR, (void*)idatas);

This causes each processor the check if it is the correct processor number, and if so read the data from the MSR:

void cpuReadMSR(void* pIData){
    pcm_msr_data_t* data = (pcm_msr_data_t*)pIData;
    volatile uint cpu = cpu_number();
    if(data->cpu_num == cpu)
    {
        data->value = RDMSR(data->msr_num);
    }
}

My question is: is turning off interrupts (via however mp_rendezvous_no_intrs does it) enough to cause the thread running the cpuReadMSR function to stay on the same CPU the whole time? If it is not, I worry about the following failure scenario:

  1. The cpu reads its numerical id with cpu_number(), decides that it is the correct CPU, and starts to read the MSR.
  2. The thread is preempted by the scheduler and moved to a different CPU.
  3. The MSR is read, but now is read from a different CPU, thus giving the wrong value.
Was it helpful?

Solution

Disabling interrupts disables ALL interrupts, not just some of them. This includes the timer interrupt, which is what normally allows a running thread to be preempted.

While interrupts are disabled, nothing (short of something crazy like a CPU exception) can interrupt your code from running, start to finish, on a single CPU.

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