Question

I want to get the VHDL simulation time of a model with a testbench. I work in ModelSim and know that the profiler of ModelSim supports performance analyzation, but it is not the information I want.

The time consuming not means the simulation steps, it is the real time running on my computer. I am looking for sentences in VHDL or commands in ModelSim or other third party tools.

Was it helpful?

Solution

Modelsim has a tcl interpreter running, so you can use that.

The clock seconds function is probably a good start, store the value at the beginning and at the end and subtract them.

TCL tutorial starts here.

For example (Caveat lector: I'm no TCL expert, and it's been a long time since I wrote any at all :)

set start [clock seconds]      # store the start time
run -all                       # run the simulation assuming it terminates when finished!
set finish [clock seconds]     # store the end time
puts [ expr {finish - start} ] # print out the difference

OTHER TIPS

You can also use this:

set sim_time [time {run -all}]

It will give you the time for the simulation in microseconds.

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