Modelsim: how to setup 27 MHz clock

Question

I want to setup a 27 MHz clock signal in ModelSim. I usually setup a clock by right clicking that signal -> clock -> setup period. For example, 50 MHz clock -> 20 ns or I used the force statement.

Because the 27 MHz clock is special, it is not a integer period, if I setup the clock with a appx value, it always having timing issues.

So, how do I setup this clock?

Answer 1

Your clocks are asynchronous. You will always have "timing issues" - if your two clock edges come very close to each other (as they inevitably will sometimes) some of your flops will exhibit metastability.

You need to resynchronise your 27 MHz domain signals to the 50 MHz domain, accept and mitigate for the fact that occasionally the synchronisation will be wrong. There are techniques to reduce the value of "occasionally" to as small a value as you think is appropriate for your system, but you'll never get rid of it.

See FPGA-FAQ 0017, Tell me about Metastability.

Answer 2

If using both domains (50 MHz, 27 MHz) is a must, then you should implement synchronization circuits at each intrface between the two domains:

Signal changes_at50;
Signal read_at27;

You do not type:

read_at27 <= changes_at50;

But attach them through a sync circuit. (Or an async FIFO.)

Synchronization circuits are usually cascaded flip-flops to minimize the meta-stabily that arises between clock domains. More cascades better reduces the meta stability, but increases data latency. It's a design choice.

Answer 3

If you are running a functional sim with only one clock, the exact period of the clock isn't too important so long as the system's inputs and outputs are clocked at the same rate.

I suggest choosing a clock period close to your target period, and scale your data sources appropriately.