ARM assembly: bad instruction "mov32"

Question

I wanted to load a 32bit constant into a register and I found a pseudo-instruction "mov32" on which can do this (mov32 pseudo-instruction). Then I write an assembly file which includes:

MOV32 r0, #0xABCDEF12

And compiled it with linaro toolchain(version 13.04):

arm-linux-gnueabihf-as -march=armv7-a -mcpu=cortex-a9 test.s -o test.o

But it failed with message:

Error: bad instruction `mov32 r0, #0xABCDEF12'

I don't know if it's the matter of unified assembly language. In case, I wrote ".syntax unified" in source code and tested again, but also failed. Does GNU toolchain support ARM pseudo-instruction like "mov32", "ldr r0, =address" etc. ? If does, how can I solve this problem? Thanks.

Answer 1

As has been mentioned by a commenter, MOV32 is a pseudo-instruction supported by ARM's own development tools. Since you're using the GNU toolchain you've got a couple of options:

You can, as dwelch mentioned, use LDR R0,=0xABCDEF12.
This is also a pseudo-instruction, which will result in the immediate constant being placed in a literal pool (small chunks of data scattered throughout the code section), which then is loaded using a PC-relative LDR.
If the constant can be encoded as imm8 ROR n (which it can't in your case, but let's say you had 0x80000000) then the LDR = psedo-instruction will be translated into a single MOV and won't add anything to the literal pool.

---

You could also use the instructions that MOV32 translates into:

MOVW R0,#0xEF12  
MOVT R0,#0xABCD

This requires an ARMv6T2 or later.

Answer 2

In the GNU assembler, one can synthesize mov32 the following way:

.macro mov32, reg, val
    movw \reg, #:lower16:\val
    movt \reg, #:upper16:\val
.endm

That'll work for ARMv7. If you'd want the "generic" behaviour (substitute it with ldr reg,=val where movw/movt don't exist), add a sprinkling of #ifdef.

(Credit where credit is due: This comes from arch/arm/mach-tegra/sleep.h of the ARM Linux kernel sources, not an invention of mine)