Reconstructing variable sized packets in verilog

Question

I am trying to reconstruct a packet that was sent via UART RS232 connections, but am not sure how to reconstruct the packet in its entirety such that the packet can be taken apart and stuff can be done using it.

The issue is that when I receive 1 byte at a time, I store that byte into a register 8 bits wide, and when I receive the next byte, I want to be able to shift the first byte by 8 bits, then add the new byte to the end. This becomes an issue as the register is now too small (8 bits vs 16 bits to hold the next byte). In addition, I cannot see a way to change the size of the register during runtime to grow and shrink depending on the size of the packet, as all registers must be static, and I also must know the exact size of the packet in order to process it.

There is the possibility of setting up an insanely large register to hold the packet, and counting how many valid bytes were copied into the register, but I am sure there is a better way to do this that I am not seeing.

All this is done using Xilinx ISE.

Answer 1

Verilog is static to mimic physical design. You will need to know the maximum number of bytes that can be supported. To know the size of the input, simply incompetent a counter as the data bytes shift. The only way to have a dynamic size is if this is for non-synthesizable behavior modeling then you can use C code to link into your design (PLI/VPI/DPI) or SystemVerilog Queues (IEEE Std 1800-2012 section 7.10). Read-up about SystemVerilog if you are interested.

The follow is a Verilog example of a large shift register:

parameter SIZE = 2**10;
reg [SIZE*8-1:0] store;
always @(posedge clk or negedge rst_n) begin
  if ( !rst_n ) begin
     counter <= 0;
     store <= {(SIZE*8){1'b0}};
  end
  else if ( push_in ) begin
     counter <= first_byte ? 0 : (counter+1);
     store <= {store[SIZE*8-1-8:0], data_in[7:0]};
  end
end

With an "insanely large register" you may need to break up the store into chunks so the simulator can handle it; some simulators cannot handle reg [2**32-1:0] store;. Sudo code example:

// ...
storeN <= {store3[SIZE*8-1-8:0], storeM[7:0]};
// ...
store1 <= {store1[SIZE*8-1-8:0], store0[7:0]};
store0 <= {store0[SIZE*8-1-8:0], data_in[7:0]};
// ...