In which hazard does cache miss fall into?

Question

There are three types of hazard in the five stage of pipeline:-

1) Control hazard : - if/jump

2) Data hazard :- RAW(read after write), WAR ( write after read), WAW (write after write)

3) structural hazard :- Structural hazards are when two instructions might attempt to use the same resources at the same time ( as in wiki)

which type of hazard does cache miss fall into?

Answer 1

Think of a hazard as a misprediction - the pipe speculatively advances each cycle, assuming there are no conflicts. It might be wrong in the cases you describe - if the next stage comes from the wrong program-counter/inst-pointer, or if the calculation source wasn't updated in time, or some resource wasn't ready in time. Now, a cache miss is not normally considered in this taxonomy, perhaps because it's implementation specific. you can say the same about varying-latency execution. You don't have the data ready so you just stall, there's no actual risk here of using stale data or fetching bogus code from the wrong path. Note that a memory access could still be RAW (load after store, in that case), and count as a data hazard just like a register-bound RAW.