What steps are necessary to pipeline a processor in VHDL?

Question

This is a homework question, obviously. I'm trying to pipeline a simple, 5 stage (IF,ID,EX,MEM,WB), single-cycle MIPS processor in VHDL. I don't need to implement forwarding or hazard detection for it. I'm just unsure of what components I need to implement.

1. Is it necessary to create D Flip-Flops for each signal?
2. The pipeline implementation here uses a for-loop for the outputs - is that something I should do?

Any tips would be much appreciated, I can't seem to find much relevant information on pipelining in VHDL.

Answer 1

What you probably want to do is create a separate entity for each stage of your pipeline and then connect the output of one stage to the input of the other.

To make sure things are pipelined correctly, you just need to make sure that each stage only does whatever processing it needs to do on the rising edge.

If you want an example, take a look at this project of mine. Specifically at the files dft_top.vhd and dft_stage[1-3].vhd. It implements a 16-point 16-bit fixed point DFT in pipelined stages.