Cannot Synthesize Signal

Question

I am a newbie when it comes to VHDL, but i am working on a counter than can manually count up and down by the push of a button.. Somehow i am only getting this error, and i dunno what i am doing wrong, all other checks are good. any suggestion?

This is the error i get:

ERROR:Xst:827 - line 101: Signal s2 cannot be synthesized, bad synchronous description. The description style you are using to describe a synchronous element (register, memory, etc.) is not supported in the current software release.

entity updown is Port (
    rst : in  STD_LOGIC;
    plus , plusin: in  STD_LOGIC;
    minus, minusin : in  STD_LOGIC;
    clk : in  STD_LOGIC;
    ud_out, ud_out2 : out  STD_LOGIC_VECTOR (3 downto 0)
);
end updown;

architecture Behavioral of updown is
    signal s  : unsigned (3 downto 0):= "0000";
    signal s2 : unsigned (3 downto 0) := "0000";
begin

    process(rst, plus, minus, clk, plusin, minusin)
    begin

        if rst='1' then
            s <= "0000";
            s2 <= "0000";
        else
            if rising_edge (clk) then 
                if plus ='1' or plusin = '1' then 
                    if s = "1001" then
                        s <= "0000";
                        if s2 = "1001" then 
                            s2 <= "0000";
                        else
                            s2 <= s2 + 1;
                        end if;                 
                    else
                        s <= s + 1;
                    end if;
                end if;
            else 
                if minus ='1' or minusin = '1' then 
                    if s = "0000" then
                        s <= "1001";

                        if s2= "0000" then
                            s2 <= "1001";
                        else 
                            s2 <= s2 - 1;
                        end if;
                    else 
                        s <= s - 1;
                    end if;             
                end if;
            end if;
        end if;

    end process;

    ud_out <= std_logic_vector(s);
    ud_out2 <= std_logic_vector(s2);

end Behavioral;

Answer 1

Your description of a synchronous process is flawed. A synchronous process has events that update only on the edge of a clock signal (although in this case there is an also an asynchronous reset behaviour )

Your sensitivity list contains more than it needs to describe a synchronous process.

Replace

process(rst, plus, minus, clk, plusin, minusin)

with

process(rst, clk )

signals will then only update when the clock transisitions, or rst changes.

Some compilers are even more picky, and might require you to change

else if rising_edge (clk)then 

to

elsif rising_edge(clk) then 

EDIT:

This should work. I've layed it out clearly so its actually easy to follow what's going on. I'd suggest you do the same in future. It make simple closure errors easy to spot

entity updown is
port ( 
   signal clk     : in   std_logic;
   signal rst     : in   std_logic;
   signal plus    : in   std_logic;
   signal plusin  : in   std_logic;
   signal minus   : in   std_logic;
   signal minusin : in   std_logic;
   signal ud_out  : out  std_logic_vector(3 downto 0);
   signal ud_out2 : out  std_logic_vector(3 downto 0)
);
end entity updown;

architecture behavioral of updown is

    signal s  : unsigned (3 downto 0);
    signal s2 : unsigned (3 downto 0);

begin

   p_counter_process: process(rst, clk)
   begin

      if rst ='1' then 
         s  <= (others => '0');
         s2 <= (others => '0');

      elsif rising_edge(clk) then 

         if plus ='1' or plusin = '1' then 

            if s = "1001" then            
               s <= "0000";

               if s2 = "1001" then 
                  s2 <= "0000";
               else
                  s2 <= s2 + 1;
               end if;                 

            else
                s <= s +1;
            end if;
        end if;

        -- you had a mismatched end if statement here. Removed

        if minus ='1' or minusin = '1' then 

           if s = "0000" then 
              s <= "1001";

              if s2= "0000" then 
                 s2 <= "1001";
              else 
                 s2 <= s2 - 1;
              end if;
           else 
              s <= s - 1;
           end if;             
        end if;

      end if;
   end process;

   ud_out  <= std_logic_vector(s);
   ud_out2 <= std_logic_vector(s2);

end architecture;