Are there any advantages to having fewer levels of wrappers in verilog?

Question

Specifically I am asking if there are any advantages of fewer levels in a hierarchical design. Ex. 5 levels vs 6.

The only pro's/ cons I am seeing are readability and maybe faster compilation depending on the tools?

Thanks!

Answer 1

Ok, so it depends how you have your constraints set up and what tool you are using. So if you allow the tool (for sure xilinx's vivado and ise does this and cadence as well) to "flatten" your design upon compilation/synthesis/pnr(place and route) there should be no difference in performance between a flattened design and a hierarchical design. this is because the tool basically ignores the boundaries of the files when trying to combine logic and place luts and what not.

If you on the other hand generate a net list or even have a tool place them out and then try and then piece them together individually you could miss out on shared logic or be stuck with a less then optimal placing or routing situation.

overall if you are interested in performance of your design, let the tool do as much as it can, the more freedom you give it the better it works. So, if you use wrappers (a good idea for human readability ) make sure to give the tool the freedom by using the flatten options.

Answer 2

I'm not going to answer your question about advantages of fewer levels of hierarchy, but I'm going to give you a general advice.

Do not think about advantages (in simulation time / area / power / anything else) of fewer levels of hierarchy when writing your design. The whole point of Front-End - Back-End separation is to allow Logic Designers to focus on functionality. The form of your design's hierarchy should be dependent upon functional considerations only (logic separation / clock domains / power domains / reset domains / etc). Create the best functionality you can, and let Back-End guys do their work (usually, they are good at it).