Why are CISC processors harder to pipeline? In what sense are some instructions "more complex" than others?

Question

According to "Computer Architecture and Organization" by Miles Murdoca and Vincent Heuring,

CISC instructions do not fit pipelined architectures very well. For pipelining to work effectively, each instruction needs to have similarities to other instructions, at least in terms of relative instruction complexity.

Why is this true? What is meant by an instruction's complexity; don't all instructions take one clock cycle to begin execution? If the instruction is reading or writing to memory then it would take longer but RISC processors read or write to memory too (of course)?

Answer 1

The "complexity" of the instructions is related to how much their size and format can vary. Take x86 IA32 (Intel 32-bits) architecture for instance, which is CISC. The size of instructions can range from 1 to 15 bytes, and their format varies a lot too (the format being how many bits are used for each field, where those bits are located and so on).

This means that you'll only know when you are done fetching the instruction once you start decoding it. Some instructions will take only a cycle to be fetched, others more, and this complicates the pipeline process.

All ARM instructions (RISC architecture), on the other hand, have exactly 4 bytes. So once you fetch 4 bytes you know that you can send those bytes for the decoding phase of the pipeline and you can immediately start fetching the next instruction.

Answer 2

What is meant by this is with CISC architectures, there are typically instructions that are relatively longer than RISC. So the scheduling is trickier. In CISC, there are often mixes of simpler instructions, and more complicated instructions that take longer. So in a pipeline there are things called hazards that can create problems for smooth pipelining. X86 Floating Point instructions would be longer than x86 load or store, for example.