Question

I am trying to use Quartus II 13.0 (Free Web Package) on Linux (Kubuntu 12.04 LTS) from the command line to generate Verilog technology netlists from Verilog RTL. I need this for a project where I compare the synthesis results produced by different tools for thousands of generated Verilog files. So using the GUI is not really an option..

For example with Xilinx Vivado I can do that using the following TCL commands:

read_verilog input.v
synth_design -part xc7k70t -top top_module
write_verilog output.v

Most ASIC tools I have worked with provide similar interfaces.

With Xilinx XST it is a bit more complicated:

1.) generation of a work.xst file:

run -ifn work.prj ..some..more..options..

2.) generation of a work.prj file:

verilog work "input.v"

3.) running synthesis:

xst -ifn work.xst

4.) generating verilog netlist from verilog binary:

netgen -w -ofmt verilog work.ngc output

But with Quartus II I can't find any documentation at all on how to use the command line tools. All I can find is documentation to the graphical IDE interface. Maybe I'm just looking in the wrong places?

So before I start poking the Quartus II IDE with strace and similar tools: Is anyone using Quartus II from the command line and can point me in the right direction?

Was it helpful?

Solution

It's very well hidden - Quartus-II Handbook Version 13.0, page 2-10 (or search ASSIGNMENT_FILES) - produces one example Makefile. It seems to have bit-rot - I've removed the ASSIGNMENT_FILES stuff, and the stamps are redundant (you can check for logfiles), but it's a start, and the basic structure works.

OTHER TIPS

For example the following shell script synthesizes the module binary_ops_00000000 from the design file binary_ops_00000000.v:

PATH=$PATH:/opt/altera/13.0/quartus/bin
quartus_map binary_ops_00000000 --source=binary_ops_00000000.v --family="Cyclone III" 
quartus_fit binary_ops_00000000
quartus_eda binary_ops_00000000 --formal_verification --tool=conformal
cp -v fv/conformal/binary_ops_00000000.vo output.v

quartus_eda supports a wide range of differend modes (see quartus_eda --help=tool for a table). The Verilog generated for Conformal LEC looks fine for my purpose.

I'd recommend running this commands in an otherwise empty directory, as they generate a bunch of files and in some cases print error messages if files from previous runs (with different setting) are found.

You can find helpful Quartus II Tcl Examples page on intel.com.

You can also use the following to get help on both all command-line arguments and Tcl functions

quartus_sh --qhelp
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