Icarus Verilog simulation : Scope index expression is not constant: i

Question

I am simulating a 16 bit MIPS netlist in Icarus Verilog. This is the error i get in testbench

mips_16_core_top_tb_0.v:144: error: Scope index expression is not constant: i
mips_16_core_top_tb_0.v:144: error: Unable to bind wire/reg/memory `uut.register_file_inst.reg_array[i]' in `mips_16_core_top_tb_0_v.display_all_regs'

Related code : 
task display_all_regs;
begin
$display("display_all_regs:");
$display("------------------------------");
$display("R0\tR1\tR2\tR3\tR4\tR5\tR6\tR7");
for(i=0; i<8; i=i+1)
$write("%d\t",uut.register_file_inst.reg_array[i]); <--- error points to this line

$display("\n------------------------------");
end
endtask

I do get this same error when i simulate the RTL too but i still get the vcd file dumped out.In case of the netlist,I dont even get the vcd file generated. Would be glad to hear your thoughts.

Answer 1

Your code looks fine, and I've just tested cross-module variable indexing of arrays in Icarus (the current version, from git) and it works.

I suspect your problem is that you're compiling mips_16_core_top_tb_0.v by itself - Icarus will give this message if you do. All source files need to be compiled together in Icarus. Some other simulators will allow you to compile this file by itself, and then only check for errors during elaboration (ie. when you run the simulation), but the way Icarus does it is how Verilog was originally intended to be used.

Answer 2

Your index in register[index] must be constant in this situation. In reg_array[i], i is a variable and not fixed. To simulate using this code you must remodel the design so that it doesn't require a variable indexed register. It may be a simulator-specific lack of support for this feature. If that is the case, you should try a different simulator.