modelsim source code

Question

The following is some modelsim code:

 begin
    tb_in_top = 0;
    #5 tb_in_top = 4'b0000;#5 tb_in_top = 4'b0001;
    #5 tb_in_top = 4'b0010;#5 tb_in_top = 4'b0011;
    #5 tb_in_top = 4'b0100;#5 tb_in_top = 4'b0101;
    #5 tb_in_top = 4'b0110;#5 tb_in_top = 4'b0111;
    #5 tb_in_top = 4'b1000;#5 tb_in_top = 4'b1001;
    #5 tb_in_top = 4'b1010;#5 tb_in_top = 4'b1011;
    #5 tb_in_top = 4'b1100;#5 tb_in_top = 4'b1101;
    #5 tb_in_top = 4'b1110;#5 tb_in_top = 4'b1111;
    #100 $finish;
  end

What does the #5 and #100 represent? Are those line numbers? Is there something wrong with this code?

Answer 1

It's not "ModelSim" code any more than something is "Visual Studio" code. It's Verilog.

The # token signifies a delay in nanoseconds.

So what this code means is:

• At t = 0, set tb_in_top to all 0's.
• At t = 5 ns, set tb_in_top to the 4-bit binary value 0000.
• At t = 10 ns, set tb_in_top to the 4-bit binary value 0001.
• At t = 15 ns, set tb_in_top to the 4-bit binary value 0010.
• At t = 20 ns, set tb_in_top to the 4-bit binary value 0011.

(... keep counting up, incrementing tb_in_top by 1 every 5 ns ...)

• At t = 80 ns, set tb_in_top to the 4-bit binary value 1111.
• At t = 180 ns, end the simulation.

Yes, Verilog has for loops, and yes, that should be one.

Addendum

The for loop would look like:

integer index;
reg [3:0] tb_in_top;
begin
    tb_in_top = 0;
    for(index = 0; index < 16; index = index + 1)
    begin
        #5 tb_in_top = tb_in_top + 4'h1;
    end
    #100 $finish;
end

Finally, note that Verilog that uses the # time-delay operation cannot be synthesized to logic; it can only be used for simulation.