Is it necessary to sign extend 0 bits in Verilog?

Question

Simple 32-bit register:

    reg32 Reg_32 (
    .in(valueA), // input 32 bits               
    .clock(clk),
    .reset(rst),
    .out(valueB) // output 32 bits  

However, valueA is defined as a 10-bit wire [9:0].

Does valueA need 22 extended 0 bits?

i.e.:

    .in({22b'0,valueA}), // 22 bits of 0 + value of wire [9:0]

or does the compiler do this in ModelSim?

Answer 1

I doubt it is necessary in most cases. But, to avoid unpredicatble behavior due to different compilers, it is safer to explicitly pad the value to the correct width. I would use replicated concatenation (as described in the IEEE Std 1800-2012, for example):

.in ({ {22{1'b0}}, valueA}),