Calculating the maximum physical rate (Nyquist performance limitation) of an ADC onboard a microcontroller

Question

I'm trying to evaluate the maximum physical rate (Nyquist performance limit) of the A/Ds integrated on board various PIC microcontrollers.

However, to do the calculation requires parameters that I'm not finding explicitly stated in the datasheets, specifically Tacq, Fosc, TAD, and divisor parameters.

I've proceeded by making some assumptions but would be helpful to have a sanity check -- am I doing the maximum physical rate calculations correctly?

For illustration purposes only, I've taken the simplest possible PIC10F220 that has an ADC. This is to focus specifically on the interpretation of Tacq, Fosc, TAD, and divisor parameters, and not to suggest that any practical functionality could be implemented on this very basic chip. (This is to Clifford's points in the comments below.)

Calculation:

Nyquist Performance Analysis of PIC10F220
- Runs at clock speed of 8MHz.
- Has an instruction cycle of 0.5us  [4 clock steps per instruction]

So:

- Get Tacq = 6.06 us  [acquisition time for ADC, assuming chip temp. = 50*C]
                      [from datasheet p34]

- Set Fosc := 8MHz     [? should this be internal clock speed ?]
- Set divisor := 4     [? assuming this is 4 from 4 clock steps per CPU instruction ?]
- This gives TAD = 0.5us          [TAD = 1/(Fosc/divisor) ]
- Get conversion time is 13*TAD   [from datasheet p31]
- This gives conversion time 6.5 us
- So ADC duration is 12.56 us   [? Tacq + 13*TAD]

Assuming 10 instructions for a simple load/store/threshold done in real-time before the next sample (this is just a stub -- the point is the rest of the calculation):

- This adds another 5 us   [0.5 us per instruction]
- To give total ADC and handling time of 17.56 us    [ 12.56us + 1us + 4us ]
- before the sampling loop repeats  [? Again Tacq ? + 13*TAD + handling ]

- If this is correct, then the max sampling rate is 56.9 ksps   [ 1/ total time ]
- So the Nyquist frequency for this sampling rate is 28 kHz.    [1/2 sampling rate]

Which means the (theoretical) performance of this system --- chip's A/D with the hypothetical real-time handling code --- is for signals that are bandlimited to 28 kHz.

Is this a correct assignment / interpretation of the data sheet in obtaining Tacq, Fosc, TAD, and divisor parameters and using them to obtain the maximum physical rate, or Nyquist performance limit, of this chip?

Thanks,

Answer 1

You're not going to be able to do much processing in 8 instructions, but assuming you're just doing something simple like storing the incoming samples to a buffer, or detecting a threshold, then your analysis looks good.

Answer 2

The actual chips I'm considering for the design are the dsPIC33FJ128MC804 (with 16b A/D) or dsPIC30F3014 (with 12b A/D).

That is an important distinction; the dsPIC ADC supports ping-pong DMA transfers of multiple channels simultaneously, so can minimise the effective software overhead per sample. That makes the calculation a somewhat different one. You need to determine from the sample rate and the DMA buffer size the time between sample buffer interrupts; that is how much processing time you have to deal with each buffer. If you are using Microchip's DSP library, it gives precise cycle time formulae for each algorithm, and block processing is considerably more efficient that sample-by-sample processing.

My last project was on a dsPIC33 with two channels sampled at 48KHz and 32word sample buffers (giving 667us to process each pair of buffers). The software processing was therefore entirely independent of the sampling since by using DMA they take place simultaneously.