Running timing simulation in modelsim

Question

I've created a small design in Verilog and now i want to run timing simulation. Since I know how to do it for VHDL files, I figured I'll do it (almost) the same way. Unfortunately, it's not that easy.

I've compiled my design and received .sdo and .vho files. But when I'm trying to run testbench, I receive error:

> vsim work.Sdesign_tb
# vsim work.Sdesign_tb
# Loading work.Sdesign_tb
# ALTERA version supports only a single HDL
# ** Fatal: (vsim-3039) C:/Users/K_impl/Sdesign_tb.v(17): Instantiation of 'sdesign' failed.
#    Time: 0 ps  Iteration: 0  Instance: /Sdesign_tb File: C:/Users/K_impl/Sdesign_tb.v
# FATAL ERROR while loading design
# Error loading design

It looks like Quartus 12.1 created VHDL files, while I want to simulate Verilog design (and Quartus supports only one VHDL at the same time). So I've tried another way, by adding .sdo files as SDF and then run simulation through "start simulation". But it also showed error (almost the same as above). So how can I bypass it? Or maybe there is another way of running timing simulation for Verilog designs?

Answer 1

To run timing simulation you may need to add altera_ver and your device libraries.

Answer 2

You seem to be compiling more than one HDL, probably VHDL and Verilog.

If you go to your project settings in Quartus and make sure it's generating a Verilog netlist, it may solve your problem. Instructions are here.