Based on your code in Dropbox, you are assigning registers in multiple always
blocks. This is illegal for synthesis and cosponsors to the Altera Quartus error message is referring to. A reg
type should only be assigned with in one always
block.
As an example, sec0
is defined in always @(posedge reset_reg)
and the code provided in your question. The code in Dropbox is even worse because you split the counter logic into 4 separate always blocks that assign sec0
.
I suggest you put all sec*
and min*
resisters one clock synchronous always block with an asynchronous:
always(@posedge clk or posedge reset_reg)
begin
if(reset_reg)
begin
// ... asynchronous reset code ...
end
else
begin
// ... synchronous counter code ...
end
end
This paper goes into detail about good verilog coding practices for synthesis: http://www.sunburst-design.com/papers/CummingsSNUG2000SJ_NBA.pdf
Other issues you will have:
- Use non-blocking (
<=
) when assigning registers. This is discussed in Cliff's paper mentioned earlier. - Get rid of the initial block. I understand some FPGA synthesizers allow it and some ignore it. It is a better practice to have an asynchronous to put everything into a known and predictable value.
- The block starting with
always @ (clk or start_reg or lap_reg or reset_reg)
has a bizarre sensitivity list and will likely give you problems. you wither want@(*)
if you want combination logic or@(posedge clk or posedge reset_reg)
for synchronous flops. - Very rarely dual edge flops are used. The line
always @ (posedge clk or negedge clk)
should bealways @ (posedge clk)
for synchronous oralways @(*)
for combination logic.