Why and when will a embedded device have both NAND and NOR?

Question

I found this snippet in the dts file of a embedded product.
Why do we have a NOR flash when we have a NAND flash?
And what is the meaning of LCS0,LCS1 which is mentioned in the localbus node below?

        localbus@a8405000 {
        #address-cells = <2>;
        #size-cells = <1>;
        compatible = "fsl,mpc8313-elbc", "fsl,elbc", "simple-bus";
        reg = <0xa8405000 0x1000>;
        interrupts = <77 0x8>;
        interrupt-parent = <&ipic>;

        // CS0 and CS1 are swapped when
        // booting from nand, but the
        // addresses are the same.
//      ranges = <0x0 0x0 0xfe000000 0x01000000    /* LCS0: NOR BOOT        */
        ranges = <0x0 0x0 0xfe000000 0x02000000    /* LCS0: NOR BOOT        */
                  0x1 0x0 0xa8000000 0x00040000    /* LCS1: NAND CONTROLLER */
//            0x2 0x0 0xa0000000 0x04000000    /* LCS2: FGPA            */
              0x2 0x0 0xa0000000 0x04000000>;  /* LCS2: FGPA            */
//            0x3 0x0 0xff000000 0x01000000>;  /* LCS3: NOR RESERVE     */

        flash@0,0 {
            #address-cells = <1>;
            #size-cells = <1>;
            compatible = "cfi-flash";
//          reg = <0x0 0x0 0x1000000>; /* 16MB */
            reg = <0x0 0x0 0x2000000>; /* 32MB */
            bank-width = <2>;
            device-width = <1>;

            u-boot@0 {
                reg = <0x0 0x80000>;
            };

            xxxx@80000 {
                reg = <0x080000 0x1000000>;
            };

            log@1080000 {
                reg = <0x1080000 0x2c0000>;
            };

            inventry@1340000 {
                reg = <0x1340000 0x20000>;
            };

            xxxxx@1360000 {
                reg = <0x1360000 0x20000>;
            };

            xxxxx@1380000 {
                reg = <0x1380000 0x20000>;
            };

            xxxxx@13a0000 {
                reg = <0x13a0000 0x20000>;
            };

            reserve-nor1@13c0000 {
                reg = <0x13c0000 0xc40000>;
            };

            dummy1@2000000 {
                reg = <0x2000000 0x0>;
            };

            dummy2@2000000 {
                reg = <0x2000000 0x0>;
            };
        };

        nand@1,0 {
            #address-cells = <1>;
            #size-cells = <1>;
            compatible = "fsl,mpc8313-fcm-nand",
                         "fsl,elbc-fcm-nand";
            reg = <0x1 0x0 0x40000>; /* NAND CONTROLLER 256KB */

            dtb-0@0 {
                reg = <0x0 0x20000>;
            };

            kernel-0@20000 {
                reg = <0x20000 0x400000>;
            };

            rootfs-0@420000 {
                reg = <0x420000 0x099e0000>;
            };

            dtb-1@9e00000 {
                reg = <0x09e00000 0x20000>;
            };

            kernel-1@9e20000 {
                reg = <0x09e20000 0x400000>;
            };

            rootfs-1@a220000 {
                reg = <0x0a220000 0x099e0000>;
            };

            internal@13c00000 {
                reg = <0x13c00000 0x6400000>;
            };

            xxxx-log@1a000000 {
                reg = <0x1a000000 0x6000000>;
            };
        };
    };

I completely do not get what the below snippet means

        // CS0 and CS1 are swapped when
        // booting from nand, but the
        // addresses are the same.
//      ranges = <0x0 0x0 0xfe000000 0x01000000    /* LCS0: NOR BOOT        */
        ranges = <0x0 0x0 0xfe000000 0x02000000    /* LCS0: NOR BOOT        */
                  0x1 0x0 0xa8000000 0x00040000    /* LCS1: NAND CONTROLLER */
//            0x2 0x0 0xa0000000 0x04000000    /* LCS2: FGPA            */
              0x2 0x0 0xa0000000 0x04000000>;  /* LCS2: FGPA            */
//            0x3 0x0 0xff000000 0x01000000>;  /* LCS3: NOR RESERVE     */

Answer 1

NOR-flash is slower in erase-operation and write-operation compared to NAND-flash. That means the NAND-flash has faster erase and write times. More over NAND has smaller erase units. So fewer erases are needed. NOR-flash can read data slightly faster than NAND.

NOR offers complete address and data buses to randomly access any of its memory location (addressable to every byte). This makes it a suitable replacement for older ROM BIOS/firmware chips, which rarely needs to be updated. Its endurance is 10,000 to 1,000,000 erase cycles. NOR is highly suitable for storing code in embedded systems. Also the support for XiP(eXecute in Place) makes it a very attractive choice to load the initial boot-loader from (even before initialising DDR).

NAND-flash occupies smaller chip area per cell. This maker NAND available in greater storage densities and at lower costs per bit than NOR-flash. It also has up to ten times the endurance of NOR-flash. NAND is more fit as storage media for large files including video and audio. The USB thumb drives, SD cards and MMC cards are of NAND type.

NAND-flash does not provide a random-access external address bus so the data must be read on a block-wise basis (also known as page access), where each block holds hundreds to thousands of bits, resembling to a kind of sequential data access. This is one of the main reasons why the NAND-flash is unsuitable to replace the ROM, because most of the microprocessors and microcontrollers require byte-level random access.

Checkout Table 1 in this document illustrating the comparative merits of each.

Answer 2

LCSx refers to "Local Chip Select x". These are signals on a bus that when set will cause a chip to respond to data requests on that bus. So by setting LCS0 on flash chip will respond to CPU data requests and by setting LCS1 another chip will respond (or something like that). Think of them as an extra address bits.

NOR flash tends to get used for BIOS and bootroms because it is usually "error free", whereas use of NAND may require a software layer to provide error correction (which you wont have until a bootrom has loaded...).

It looks like you can choose to boot from NAND or NOR by swapping over a couple of chip select lines. That way when the CPU puts its boot address on the address lines of the bus you control which chip responds, the NOR or the NAND.