VHDL code in NCLaunch giving errors not given in Xilinx

Question

I am trying to make a dataflow design for a comparator in VHDL. It compiles and simulates fine in Xilinx, but I have to use Cadence/NCLaunch. When I copied the same code to gedit and ran it, it gives an error about a semicolon.

my code is :

library ieee;
use ieee.std_logic_1164.all;
-----------------------------------------------------
entity Comparator is
port(   A:    in std_logic_vector (3 downto 0);
        B:    in std_logic_vector (3 downto 0);
        AeqB:  out std_logic;
    AltB:  out std_logic;
    AgtB:  out std_logic);
end Comparator;


architecture dataflow of Comparator is

signal AeB : std_logic;
signal AlB : std_logic;
signal AgB : std_logic;
signal i : std_logic_vector (3 downto 0);
signal j : std_logic_vector (3 downto 0);

begin
    B1: BLOCK BEGIN   
        AeB <= i(3) AND i(2) AND i(1) and i(0);
        AgB <= j(3) or j(2) or j(1) or j(0);
        AlB <= AeB nor AgB;
    END BLOCK B1;


    B2: BLOCK BEGIN
            i <= a xnor b;
    END BLOCK B2;


    B3: BLOCK BEGIN
        j(3) <= (not b(3)) and a(3);
        j(2) <= i(3) and not b(2) and a(2);
        j(1) <= i(3) and i(2) and not b(1) and a(1);
        j(0) <= i(3) and i(2) and i(1) and not b(0) and a(0);       
    END BLOCK B3;


    B4: BLOCK BEGIN
        AeqB <= AeB;
        AltB <= AlB;
        AgTB <= AgB;
    END BLOCK B4;


end dataflow;

...and the error I get is:

i <= a xnor b;
       |
ncvhdl_p: *E,EXPSMI (/ugrad/syedhuq/ECE425/Lab2/Comparator.vhd,29|11): expecting a semicolon (';') [9.5.1].

As far as I can tell, I have a semicolon there...also if I replace the statement with four individual statements like

i(n) <= a(n) xnor b(n); //[n = 1, 2, 3, 4], 

i get the same error 4 times. Can anyone help me out with this??

Also, it compiles fine in Synopsys (VCSMX) and so does the testbench file, but during the linking process it tells me :

Design unit 'COMPARATOR(BEHAVE)' from library '.' cannot be opened for 
  reading.
  Possible causes:
  [1] Incorrect logical to physical mapping in synopsys_sim.setup file. 
  [2] Intermediate file generation was prematurely terminated during analysis.
  Reanalyze the design unit and resolve any errors that occur during analysis.

the relevant line from the testbench code is:

for x1: Comparator use entity work.Comparator(Behave);

Answer 1

I'm not familiar with Cadence/NCLaunch, but knowing your code analyzes correctly in an IEEE 1076-1993 compliant tool, and noting where error is (you indicated character position 11 in line 29, noting it appears to be character position 17), I'd say off hand it either doesn't have "xnor" un-commented in package std_logic_1164 (both the specification and the body), or it's a VHDL87 compliant tool, or there's some missing tool set or command line argument to use use the proper std_logic_1164 package.

In the distributed source for std_logic_1164, available from http://standards.ieee.org/downloads/1076/1076.2-1996/

-- --------------------------------------------------------------------
--  version | mod. date:| 
--   v4.200 | 01/02/92  | 
-- --------------------------------------------------------------------

You'll find that xnor is commented out by default, when after VHDL92 (-1993, don't ask) was approved it was supposed to be un-commented.

--  -----------------------------------------------------------------------
--  Note : The declaration and implementation of the "xnor" function is
--  specifically commented until at which time the VHDL language has been
--  officially adopted as containing such a function. At such a point, 
--  the following comments may be removed along with this notice without
--  further "official" ballotting of this std_logic_1164 package. It is
--  the intent of this effort to provide such a function once it becomes
--  available in the VHDL standard.
--  -----------------------------------------------------------------------
--  function "xnor" ( l, r : std_logic_vector  ) return std_logic_vector;
--  function "xnor" ( l, r : std_ulogic_vector ) return std_ulogic_vector;

9.5.1 refers to Conditional signal assigns in IEEE=1076-1993.

The analyzer is acting like it doesn't recognize xnor as a operator and if you look in -1993 7.2.1 Logical operators:

The logical operators and, or, nand, nor,xor, xnor, and not are defined for predefined types BIT and BOOLEAN. They are also defined for any one-dimensional array type whose element type is BIT or BOOLEAN.

Which tells us in an IEEE 1076-1993 compliant tool the declarations for xnor would come from the std_logic_1164 package.

I had a quick gander through some NCSIM, etc. online user guides and tutorials and didn't see anything relating to the problem. It's likely the std_logic_1164 package hadn't had xnor un-commented in both the declaration and body.

The issue may be the the providence (age) or the particular tool copy you are using and may require sysadmin help to correct. In the mean time you can either write your own xnor function (shown), if running into any difficulties try and use not( a xor b) instead.

architecture dataflow of Comparator is


function "xnor"  ( l : std_logic; r : std_logic ) return ux01 is
begin
    return not (l xor r);
end "xnor";

signal AeB : std_logic;
signal AlB : std_logic;
signal AgB : std_logic;
signal i : std_logic_vector (3 downto 0);
signal j : std_logic_vector (3 downto 0);

begin

Also see Weird XNOR behaviour in VHDL