Compiler bug, or misunderstanding of SystemVerilog? Undeclared port type works in simulation

Question

I have a module with a number of input logic and output logic ports, and one port that should be input foo::bar, where foo is a package, and bar is an enum. But, I left off the input, so it's just plain foo::bar. And yet, it still works in simulation (tests pass, and you can see on waveforms that the value is being transmitted correctly).

From the LRM, we have:

inout_declaration ::= 
  inout port_type list_of_port_identifiers 
input_declaration ::= 
  input port_type list_of_port_identifiers 
  | input data_type list_of_variable_identifiers 
output_declaration ::= 
  output port_type list_of_port_identifiers 
  | output data_type list_of_variable_port_identifiers 
interface_port_declaration ::= 
  interface_identifier list_of_interface_identifiers 
  | interface_identifier . modport_identifier list_of_interface_identifiers 
ref_declaration ::= 
  ref data_type list_of_port_identifiers 
port_type ::=  
  [ net_type_or_trireg ] [ signing ] { packed_dimension } 

It's clearly not inout_dec, input_dec, output_dec, or ref_dec. Looking deeper at the LRM, net_type_or_trireg is supply0 | supply1 | tri | triand | trior | tri0 | tri1 | wire | wand | wor or tri, and it's not those.

Could it be an interface_port_dec? Well, interface_identifier ::= identifier and enum_identifier ::= identifier. But, sure := isn't symmetric and transitive, so it's not true that interface_identifier := enum_identifier.

What am I missing here?

Answer 1

It is begin defined as an inout.

See IEEE Std 1800-2012 § 23.2.2.3 Rules for determining port kind, data type, and direction

For the first port in the port list:
— If the direction, port kind, and data type are all omitted, then the port shall be assumed to be a member of a non-ANSI style list_of_ports, and port direction and type declarations shall be declared after the port list.
Otherwise:
— If the direction is omitted, it shall default to inout.
— If the port kind is omitted, it shall be determined as specified below.
— If the data type is omitted, it shall default to logic except for interconnect ports which have no data type.

In the same section after some some examples,t the LRM states:

For subsequent ports in the port list:
— If the direction, port kind and data type are all omitted, then they shall be inherited from the previous port. If the previous port was an interconnect port, this port shall also be an interconnect port.
Otherwise:
— If the direction is omitted, it shall be inherited from the previous port.
— If the port kind is omitted, it shall be determined as specified above.
— If the data type is omitted, it shall default to logic except for interconnect ports that have no data type.