Shifting a Concatenate Register

Question

Ive been doing verilog HDL in quartus II for 2 month now and have not synthesized any of my codes yet. I am struggling to code a fractional division circuit. Of course theres a lot of problems...

I would like to know how do I concatenate two registers to form a larger register that I can shift to the right where the shifting of the data would occur at every positive edge of the clock pulse... The data in the newly created register has 3 zeros (MSB) followed by 4 data bits from another register called divider.
For example B=[0 0 0]:[1 0 1 0]

I have tried the following

module FRACDIV (divider,clk,B,START,CLR);

input       [3:0]  divider;
input           START, CLR, clk;
output      [6:0] B;

    reg [6:0]       B;


always @ (posedge clk)
    begin
        B = {3'd0, divider};
            if (START == 1'b1)
        begin
        B=B+B<<1;
        end
    end

endmodule

Any help would be deeply appreciated as I've been trying to figure this out for 5 hours now...

---

Mr. Morgan,

Thank you for the tips. The non-blocking statement did help. However the code would not shift perhaps because B is always reinitialized at every clock pulse as it is outside the if statement.

With a fresh new day and a fresh mind and owing to your suggestion using the non-blocking statement I tried this...

module FRACDIV(divider,clk,B,START,CLR);
input       [3:0] divider;
input           START, CLR, clk;
output      [6:0] B;

    reg [6:0] B;

    always @ (posedge clk) 
    begin
      if (START) begin
        B <= {3'b0, divider};
      end
      else begin
         B <= B <<1;
      end
    end
endmodule

The if statement loads data into B whenever START is HIGH. When START is LOW, the data shifts at every positive edge of the clock. Is there anyway to make the data in B to start shifting right after loading it with the concatenated data without the if statement?

Just curious and I still do not feel this code is the most efficient.

Answer 1

When implying flip-flops it is recommended to use <= non-blocking assignments.

When declaring outputs you should also be able to delcare it as a reg, unless you are stuck using a strict verilog-95 syntax.

module FRACDIV (
  input       [3:0] divider,
  input             START, CLR, clk,
  output reg  [6:0] B
);

always @ (posedge clk) begin 
  B <= {3'd0, divider};
  if (START == 1'b1) begin 
    B<=B+B<<1;  //This will overide the previous statement when using `<=`
  end 
end
endmodule

This will simulate in the same way that your synthesised code will perform on the FPGA.