Cases throwing unexpected when

Question

I'm making a statemachine in VHDL. My case is throwing an unexpected when error

case state IS
            --state 1 A
            WHEN s0=>
                --Half step
                if(FULL = '0' AND RIGHT = '1') then
                    state <= s1;
                else if (RIGHT = '0') then
                    state <= s7;
                end if;

                --Full step
                if (FULL = '1' AND RIGHT = '1') then
                    state <= s2;
                else if (RIGHT = '0') then
                    state <= s6;    
                end if;

            --State 2 A&B
            WHEN s1=>
                if(RIGHT = '0') then
                    state <= s0;
                else if (RIGHT = '1') then
                    state <= s2;
                end if;

However, when running a syntax check with xilinx ISE I'm greeted with a

ERROR:HDLParsers:164 Line 72. parse error, unexpected WHEN, expecting END

This happens 8 times in total. What am I doing wrong?

Answer 1

The if and end if are not balanced, so you will have to close the if with some more end if, or use elsif instead of else if.

You write:

if ... then
  ...
else if ... then
  ...
end if;

Even through your indentation shows this like balanced, it is not, since the right indentation would be:

if ... then
  ...
else 
  if ... then
    ...
  end if;

Then it is clear that the if and end if are not balance.

If you use elsif you can write it as:

if ... then
  ...
elsif ... then
  ...
end if;

Answer 2

Once you have done the correction suggested by @MortenZdk, you need to also consider your logic. In the following, you will never go to state s7 because the assignments done for full step will always over write it.

    WHEN s0=>
        --Half step
        if(FULL = '0' AND RIGHT = '1') then
            state <= s1;
        elsif (RIGHT = '0') then
            state <= s7;
        end if;

        --Full step
        if (FULL = '1' AND RIGHT = '1') then
            state <= s2;
        elsif (RIGHT = '0') then
            state <= s6;    
        end if;

For this example, I would recommend rewriting it as a nested if then else. It is also a good practice to avoid the final elsif.

    WHEN s0=>
       if (FULL = '1') then  -- Full Step
          if (RIGHT = '1') then
            state <= s2;
          else 
            state <= s6;
          end if;

       else            --Half step   
          if (RIGHT = '1') then
            state <= s1;
          else 
            state <= s7;
          end if;
       end if;

I like the active high checks since with VHDL-2008 once your synthesis tool supports it, you will be able to leave off the "= '1'". Ie:

   if FULL then  -- Full Step
      if RIGHT then

Alternately you could concatenate them into a variable and and use a case statement. My suggestion is to always code for readability.