How do I specify weak feedback inverter in Verilog

Question

I have a normal inverter IV1(.in(a), .out(b)) driven by a controlled inverter IV0(.c(ctrl),.in(d),.out(a)). For IV0, When ctrl is 1, output is driven. Otherwise, it is left floating.

In the meantime, there is a weak feedback inverter IVW(.in(b), .out(a)).

The value of node a is driven by IV0 when ctrl is 1. When ctrl is 0, node a is driven by weak feedback inverter.

When IV0 drives node a, weak feedback inverter IVW is driving node a as well. If they drive node a to different values, verilog will produce X.

How can I write this in verilog?

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original answer

module buf(input d,ctrl, output b);
  reg a,b;
  always @ (d or ctrl) begin
    if(ctrl==1) begin
      a=~d;
      b=~a;
    end
    else begin
      a=~b;
      b=~a;
    end
  end
endmodule

commented by Morgan

This will not work the same way after synthesis as your current RTL simulation. You really need to use always @* to ensure RTL and gate level will match.

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Answer 1

To specify a weak inverter:

not (weak1,weak0) u0 (out0,in1);

For more info.

IV0(.c(ctrl), .in(d), .out(a)); //out is z when crtl==0
IV1(          .in(a), .out(b));     
IVW(          .in(b), .out(a)); //out has weak drive

When ctrl is 1 we only really have this in play :

IV1(          .in(a), .out(b));     
IVW(          .in(b), .out(a));

This is a timing loop likely resulting in an unstable oscilator.