Makefile, macro modifiers

Question

I relatively new to writing make files and could use some pointers. What I'm trying to achieve is probably fairly basic but after searching the web I fail to understand how.

I would like to compile a set of object files from a src directory into a build directory and my naive idea were to define the set of source files as a macro, use macro modifiers to create a macro for the object files (so that these are properly compared to the source files when recompiling. My current scheme fro creating the object files macro looks as:

SRCDIR = /some/dir/
BUILDDIR = /some/dir/
CSRC = \
        $(SRCDIR)f1.c \
        $(SRCDIR)f2.c \

OSRC = $(CSRC,.c=.o,F,<$(BUILDDIR))

all:
    @echo $(OSRC)

where the all rule is simply put in to check if the object files macro is set properly. Unfortunately it is not, instead it is empty. Replacing

OSRC = $(CSRC,.c=.o,F,<$(BUILDDIR))

by

OSRC = $(CSRC:.c=.o)

does give me a macro of object files but not with the proper directories. Thus insight on how to modify my file to get what I want would be appreciated. (I'm using GNU Make 3.82)

Answer 1

I'm not sure where you got $(CSRC,.c=.o,F,<$(BUILDDIR)); there's nothing even remotely like that syntax in GNU make.

The statement $(CSRC:.c=.o) replaces all the .c suffixes with .o, but that doesn't help you because you also want to replace the directory.

You should use the $(patsubst ...) function:

OSRC = $(patsubst $(SRCDIR)%.c,$(BUILDDIR)%.o,$(CSRC))