typedef
is a SystemVerilog keyword, not Verilog.
To enable SystemVerilog on Modelsim you need to add the -sv
compile option and/or rename the file to with a .sv
extension.
Pregunta
I don not know what is wrong here. I use a modelsim SE 6.5b. Then when I use "typedef" I get a syntax error.
`timescale 1ns/10ps
// Type define a struct
typedef struct {
byte a;
reg b;
shortint unsigned c;
} myStruct;
module typedef_data ();
// Full typedef here
typedef integer myinteger;
// Typedef declaration without type
typedef myinteger;
// Typedef used here
myinteger a = 10;
myStruct object = '{10,0,100};
initial begin
$display ("a = %d", a);
$display ("Displaying object");
$display ("a = %b b = %b c = %h", object.a, object.b, object.c);
#1 $finish;
end
Solución
typedef
is a SystemVerilog keyword, not Verilog.
To enable SystemVerilog on Modelsim you need to add the -sv
compile option and/or rename the file to with a .sv
extension.
Otros consejos
Your code works fine on Modelsim 10.1d. See example on EDA Playground (I had to add an endmodule
but it's otherwise unmodified).
I'd suggest checking your compile flags to ensure you're enabling support for SystemVerilog during compilation.