Verilog code error

Question

I am getting error in this code. The code is for a 4 bit comparator. The error is that I get "unspecified" output in the out1 port.

Please help.

module bitCompare(num1,num2,out1,out2);

    parameter n = 3;

    output out1;
    output out2;
    input  [n:0] num1;
    input  [n:0] num2;

    wire [n:0] eq;
    wire x0,x1,x2,x3;
    wire a,b,c,d;
    wire an;

    // Comparator in structural mode
    xnor xn1(x0,num1[0],num2[0]);
    xnor xn2(x1,num1[1],num2[1]);
    xnor xn3(x2,num1[2],num2[2]);
    xnor xn4(x3,num1[3],num2[3]);
    and  a1(out2,x0,x1,x2,x3);
    not  n1(an,num1[3]);
    and  a2(a,an,num2[3]);
    not  n2(an,num1[2]);
    and  a3(b,x3,an,num2[2]);
    not  n3(aN,num1[1]);
    and  a4(c,x3,x2,an,num2[1]);
    not  n4(an,num1[0]);
    and  a5(d,x3,x2,x1,an,num2[0]);
    or   o1(out1,a,b,c,d);
endmodule

module Testbench;

    reg [3:0] numb1, numb2;
    wire outp1;
    wire outp2;
    bitCompare c(numb1, numb2,outp1,outp2);

    initial
    begin
    //case 0
        numb1 <= 4'b0000;
        numb2 <= 4'b0001;  #20;  $display("isEqual= %b\t",outp2); $display("less= %b\n",outp1);
        numb1 <= 4'b1111;
        numb2 <= 4'b1111;  #10;  $display("isEqual= %b\t",outp2); $display("less= %b\n",outp1);
        numb1 <= 4'b1000;
        numb2 <= 4'b1010;  #10;  $display("isEqual= %b\t",outp2); $display("less= %b\n",outp1);
        numb1 <= 4'b0111;
        numb2 <= 4'b0111;  #10;  $display("isEqual= %b\t",outp2); $display("less= %b\n",outp1);
    //case2
    end
endmodule

Answer 1

Verilog simulates almost everything in parallel. When a net has multiple drivers, the values values need to be resolved. If the drivers are all the same value, then the output will have a known value. If the driving values do not match, the output is X. There is not last assignment wins except within an blocking statements.

Verilog allows multiple drivers on a net and it is not going to warn you about it. Insuring a single-driver can be done by switching to SystemVerilog and assign values within always_comb, always_ff, and always_latch blocks.