Verilog combinational logic

Question

I'm attempting to implement the following logic equation in Verilog:

A1'*B1 + A1'*A0'*B0 + A0'*B1*B0

where A1, A0, B1, B0 are inputs, and ' indicates negation. This is my first go at coding in Verilog, and I'd like to see if I'm on the right track. Any help would be much appreciated.

This is what I have worked up:

module HW7P1 ( A1, A0, B1, B0, O );
     input A1, A0, B1, B0;
     output reg O;
    
     always @( A1 or A0 or B1 or B0 )
     begin
             if( !A1 && B1 ) begin
                 O <= 1;
         end else if( !A1 && !A0 && B0 ) begin
                 O <= 1;
         end else if( !A0 && B1 && B0 ) begin
                 O <= 1;
         end else begin
                 O <= 0;
         end
     end
endmodule

Have I done anything wrong here?

Answer 1

I believe the following continuous assignment is equivalent to your logic equation:

wire O = (!A1&B1) | (!A1&A0!&B0) | (!A0&B1&B0);

You should create a testbench to prove that this is the logic you desire.