verilog compiler error: near ";": syntax error, unexpected ';' [closed]

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I'm trying to write traffic light FSM code for green, yellow, red which has a delay of 20 time units. It goes from Green-yellow-red-yellow- green. This is my code and I'm getting error while using 'repeat' for delay.

Errors:

Error: C:/Users/Desktop/Design/tlights.v(33): near ";": syntax error, unexpected ';'
Error: C:/Users/Desktop/Design/tlights.v(37): near ";": syntax error, unexpected ';'
Error: C:/Users/Desktop/Design/tlights.v(44): near ";": syntax error, unexpected ';'

`define delay 20;
 module tlights(clk, rst, y);

 input clk, rst;
 output [1:0]y;
 reg [1:0]y;
 reg [1:0] cs,ns;
 integer p;

 parameter red = 2'd2;
 parameter orange = 2'd1;
 parameter green = 2'd0;

 parameter s0 = 2'd0;
 parameter s1 = 2'd1;
 parameter s2 = 2'd2;


 always@(posedge clk or negedge rst)
 begin
 if(!rst)
 begin
  cs<=s0;
 end
 else
  cs<=ns;
 end

 always@(cs)
 begin
 case(cs)
        s0: begin 
             repeat (`delay) @(posedge clk); // <-- Error here
                ns=s1;
             end
        s1: begin
             repeat (`delay) @(posedge clk); // <-- Error here
             if (p==0)
                  ns =s2;
                else 
                 ns=s0;
            end
        s2:    begin 
              repeat (`delay) @(posedge clk); // <-- Error here
                 ns<=s1;
               end
        default: ns<=s0;
      endcase
   end 

  always@ (cs)
  begin
    case(cs)
      s0:begin 
          y<=2'b00; 
          p<=0;
         end
      s1:y<=2'b01; 
      s2:begin 
         y<=2'b10; 
         p<=1;
         end         
  endcase
 end
 endmodule

Answer 1

The problem is with your `define statement. `define is similar to #define in C/C++. The statements do literal substitution and the terminator is end of line, not a semi-colon. repeat (`delay) means repeat ( 20; ). Remove the ; and it will simulate.

Even with with the correction it will not synthesize. Blocking statements (i.e. @,#, and wait) are not allowed inside combinational logic. To be synthesizable, you'll need to add some flip-flops for a counter. Your next state and next counter combinational logic should look something like the following:

always @* begin
  // default value
  ns = cs;
  next_counter  = counter + 1;
  // update value
  case(cs)
    s0: begin
      if (counter >= `delay) begin
        ns = s1;
        next_counter = 0;
      end
    end
   /* ... */
  endcase
end

Also, remember to assign flops with non-blocking (<=). Blocking (=) for assigning combinational logic.