$fatal
is a run-time system call, not a compile-time fatal as mentioned by toolic. I don't think you can stop the compile unless you have a compile error. In your sample code you are getting close to what you want by hiding part of the code, but the compile does not terminate and you don't print the right message.
I am not aware of any standard Verilog/SystemVerilog construct for printing a customized message during the compile time. GCC for example, has #error
for this purpose. However, some synthesis tools, like Synopsis Design Compiler do print the output of $display
messages during elaboration time. The $display
still needs to be inside an always
block. If you also deliberately place an elaboration error when MACRO0 and MACRO1 are not defined, you may be able to terminate the synthesis.
For example, in the following, a dummy module is instantiated without defining its body:
`ifdef MACRO_0
// Some code
`elsif MACRO_1
// Some other code
`else
logic a;
always $display("MACRO_0 or MACRO_1 must be set for compilation");
DEFINE_MACRO0_OR_MACRO1 dummy (.in(a));
`endif
this will generate the following elaboration message:
$display output: MACRO_0 or MACRO_1 must be set for compilation
...
Information: Building the design 'DEFINE_MACRO0_OR_MACRO1'. (HDL-193)
Warning: Cannot find the design 'DEFINE_MACRO0_OR_MACRO1' in the library 'WORK'. (LBR-1)
Warning: Unable to resolve reference 'DEFINE_MACRO0_OR_MACRO1' in 'TEST'. (LINK-5)
0