VHDL Verilog Integer Arrays Ports

Question

I am working on a project for the FPGA implementation of the Breakout Game. In this game, we have to break the bricks using a ball and a paddle. Some bricks may break on multiple contacts with the ball. For this, I am using an integer array to represent the number of hits required to break a particular brick. eg (2,0,1,2) represents a brickk which needs 2 hits to be broken followed by a broken brick followed by a brick which needs a single hit to be broken et al.

Also, I have done all my coding in VHDL but in order to output the results onto the VGA screen, I am using Verilog.

In VHDL, I have declared a type for an integer array in a package as follows:

package mytypes_pkg is
    type int_array is array (0 to 39) of integer;
end mytypes_pkg;

then in my ball motion controlling file, I have imported work.mytypes_pkg.all and then have:

brickout:out int_array;

which contains the current state of all the bricks in the game. This array has to be passed to my Verilog file where all the VGA Display generation has to take place. There, I tried

input [39:0]    bricki;

but it gives me the error

"Different types for port 'brickout' on entity and component for 'mainc'"

How can I rectify this error and do what I want to do? Is there some way of telling Verilog that bricki is also of type int_array? And do I need to import work.mytypes_pkg.all in Verilog too?

Answer 1

In SystemVerilog you can use typedef to define your own types, e.g.

typedef int [N-1:0] mytype;

and this way build exactly what you want. Define your types in a package and then import it:

import pkg_keccak::mytype;
...
mytype int_table;