Makefile: set-based rule selection

Question

In a Makefile, I would like to have a variation for the usual generic rule for compilation

%.o: %.cpp
    $(CC) -c $(CC_FLAGS) $< -o $@

but I would like to discriminate between two rules based on the membership of the target in two different sets:

# Rule A - use if target object in the set (some_obj_1.o, some_obj_2.o)
%.o: %.cpp
    $(COMPILER_A) -c $(CC_FLAGS_A) $< -o $@

# Rule B - use if target object in the other set (another_obj_1.o, another_obj_2.o)
%.o: %.cpp
    $(COMPILER_B) -c $(CC_FLAGS_B) $< -o $@

I.e. how to cause make to use rule A for a target file in set A (e.g. some_obj_1.o) and rule B for a target file in set B (e.g. another_obj_1.o)?

Answer 1

Use static pattern rules:

SET_A := some_obj_1.o some_obj_2.o
SET_B := another_obj_1.o another_obj_2.o

$(SET_A): %.o : %.cpp
    ...

$(SET_B): %.o : %.cpp
    ...