Carry/auxiliary flag functions in x86 ALU

Question

I'm trying to create a 8086 processor in Verilog, and I have a better-than-average fundamental understanding of most of the architecture (and can get along happily once I get past this point), but I can't seem to wrap my head around how the Carry and Auxiliary flags function in the ALU.

I understand that CF is triggered upon an addition or subtraction (in which case it's called borrow) that would cause the result to be larger than the bit width of the ALU.

But, how would I write Verilog code for addition and subtraction that would allow me to write to the FLAGS[0] (CF) bit and then re-access it to continue the operation? Can anyone give me examples that I can deconstruct?

Also, this is even more of a n00b question, but how is it that an ALU with carry operation can support creation of a 17-bit number if the SI and DI registers are only 16 bits in width? Where does that extra bit go or what gets done with it? What happens if multiplication creates that same bit overflow?

Many apologies for the novice-level questions. I almost feel like I'm set to get yelled at for some obvious ignorance or lack of understanding with regards to this. Many thanks to anyone who can help and give code lines for understanding to elucidate this for me.

Answer 1

I don't quite know what you mean and then re-access it to continue the operation, but if you're just asking how you can generate a carry bit from a 16 bit addition/subtraction, this is one way to do it (use concatenation to write result to two different registers):

always @ posedge clk begin
  if(add_with_carry)
    {CF[0], result[15:0]} <= a[15:0] + b[15:0];
  else if(sub_with_carry)
    {CF[0], result[15:0]} <= a[15:0] - b[15:0];
  else if(add_without_carry)
            result[15:0]  <= a[15:0] + b[15:0];
  else if(sub_without_carry)
            result[15:0]  <= a[15:0] - b[15:0];
end

This is also basically the same thing as writing the result to a 17 bit register, and then just designating result[16] as the carry flag.